Integrated circuits have progressed to advanced technologies with high packing densities and smaller feature sizes, such as 45 nm, 32 nm, 28 nm and 20 nm. In these advanced technologies, three dimensional transistors each having a multi-fin structure are often desired for enhanced device performance. However, existing methods and structures for such structures have various concerns and disadvantages associated with device quality and reliability. For example, various defects or resides can be introduced during the polysilicon etch. In another example, a capacitor structure is not easily integrated with a fin transistor while still maintaining a capability of tuning its capacitance in an acceptable range. Furthermore, the fabrication cost is higher due to additional process steps, such as the need for an additional mask to define one or more features of the capacitor. Therefore, there is a need of a structure and a method making the structure having a fin transistor and a capacitor integrated to address the above concerns.